Method and apparatus for releasing bus control by a device connected to the bus

ABSTRACT

In a digital bus, such as the IEEE 1394 serial bus, the procedure for sending data from a link layer IC onto the data bus is that the link layer IC requests access to the bus and then waits until the physical layer IC grants the desired access. Upon detecting the grant status, the link layer IC is free to send data onto the bus. But if in the meantime the link layer IC refrains from sending data onto the bus, the granted bus access will not be given up. As a consequence the bus is blocked for an indefinite time period because the bus access granted cannot be overwritten by the physical layer IC. According to the invention an additional timer function is implemented in the link layer IC. This ‘bus grant missed’ timer function controls the link layer IC in such a way that it automatically gives back the bus control to the physical layer IC after a predetermined time period has elapsed during which the link layer IC has sent no data onto the bus.

This application claims the benefit of EPO application serial No.99250060.3 filed Mar. 3, 1999, which is hereby incorporated herein byreference, and which claims the benefit under 35 U.S.C. §365 ofInternational Application PCT/EP00/01413, filed Feb. 21, 2000, which waspublished in accordance with PCT Article 21(2) on Sep. 8, 2000 inEnglish.

The present invention relates to a method and to an apparatus fortransferring data on a bus to or from a device to be controlled by saidbus, wherein bus blocking is to be avoided.

BACKGROUND

The IEEE1394 bus is a low cost, high performance serial bus. It has aread/write memory architecture and a highly sophisticated communicationprotocol. Data rates of 100, 200 or 400 Mbit/s can be transmitted innearly real time. Simultaneously, data can be transmittedbi-directionally. The first ten bits of transmitted address values referto one of up to 1023 possible IEEE1394 bus clusters. The following sixbits of the transmitted address values refer within a specific clusterto one of up to 63 nodes to which an application or device is assigned.Data between nodes can be exchanged without interaction of a hostcontroller. Devices can be connected to or disrupted from the network atany time, allowing a plug and play behaviour.

The standardised cable connection for the nodes has a length of 4.5 mand contains three twisted cable pairs of which two pairs serve for dataand control information transmission and the further pair carries supplyvoltages of 8V to 40V. Three level coding is used: HIGH (H), LOW (L),and HIGH IMPEDANCE (Z). H overrides L, L overrides Z. The characteristicimpedance is 110 Ω. There is also a version IEEE1394-1995 of the busspecification including only two twisted pairs of cables on which nopower supply voltage is present. The communication protocol has threelayers: physical layer, link layer, and transaction layer. Typically,the transaction layer is realised by firmware whereas the other layersare implemented using chip sets.

The physical layer contains analog transceivers and a digital statemachine. It handles bus auto-configuration and hot plug. It reclocks,regenerates and repeats all packets and forwards all packets to thelocal link layer. It carries out-packet framing, for example speed code,prefix, and packet end assembling. It arbitrates and transmits packetsfrom the local link layer. Available IC types are e.g. TSB11C01,TSB11LV01, TSB21LV03, and TSB41LV03 of Texas Instruments, MB86611 ofFujitsu, and 21S750 of IBM.

The link layer performs all digital logic. It recognises packetsaddressed to the node by address recognition and decodes the packetheaders. It delivers packets to higher layers and generates packets fromhigher layers. It works either isochronous for AV data use orasynchronous for control data use.

In the isochronous mode a channel having a guaranteed bandwidth isestablished. There is a defined latency. The transmission is performedin 125 μs time slots or cycles. Headers and data blocks of a packet haveseparate CRCs (cyclic redundancy check). This mode has a higher prioritythan the asynchronous data transfer mode.

The asynchronous mode is not time critical, but safe. It operates as anacknowledged service with a busy and retry protocol. Fixed addresses areused. Transmission takes place when the bus is idle. The asynchronousmode handles read request/response, write request/response, and lockrequest/ response. It performs cycle control, CRC generation andvalidation. Available link layer IC types are e.g. TSB12C01A, TSB12LV21,TSB12LV31, and TSB12LV41 of Texas Instruments, and PDI1394L11 ofPhilips.

The transaction layer implements asynchronous bus transactions:

Read request/read response

Write request/write response

Lock request/lock response

As mentioned above it can be implemented by software running on amicrocontroller, such as e.g. the 1960 of SparcLite. There may also bean AV (audio video) layer carrying out device control, connectionmanagement, timestamping, and packetising.

INVENTION

A link layer IC implements the interface to an external application,e.g. a VCR, and prepares IEEE1394 data for sending on the IEEE1394 bus,or interprets incoming IEEE1394 data packets from the IEEE1394 bus. Aphysical layer IC implements the direct electrical connection to the busand controls many functions as mentioned above, including arbitrationfor sending data on the bus. The procedure for sending data from a linklayer IC onto the bus is that the link layer IC requests access to thebus and then waits until the physical layer IC grants the desiredaccess. Upon detecting the grant status, the link layer IC is free tosend data onto the bus. But if in the meantime the link layer status haschanged, i.e. the link layer IC refrains from sending data onto the bus,the granted bus access will not be given up according to the currentIEEE1394 bus specification. As a consequence the bus is blocked for anindefinite time period because the bus access granted cannot beoverwritten by the physical layer IC. A bus lock-up is very serious andmeans that the whole bus is jammed, no other node can get access to thebus to send data.

According to the invention an additional timer function is implementedin the link layer IC. This ‘bus grant missed’ timer function controlsthe link layer IC in such a way that it automatically gives back the buscontrol to the physical layer IC after a predetermined fixed time periodhas elapsed during which the link layer IC has sent no data onto thebus. The predetermined fixed time period can be user programmable inorder to adapt it to a given bus configuration or application,respectively.

It is one object of the invention to disclose a method for avoiding busblocking in case a granted bus access in not used for sending data ontothe bus. This object is achieved by the method disclosed in claim 1.

It is a further object of the invention to disclose an apparatus whichutilises the inventive method. This object is achieved by theapparatuses disclosed in claim 3.

In principle, the inventive method is suited for transferring data on abus to or from a device to be controlled by said bus, wherein forinterfacing between the bus and said device a physical layer IC and alink layer IC are used and wherein said physical layer IC generates agrant signal in order to give to said link layer IC access to said busfor sending data onto said bus and until said link layer IC has finishedsending said data onto said bus following said grant signal, said busremains occupied by said link layer IC, wherein said link layer ICincludes a timer function which in case said physical layer IC grants tosaid link layer IC access for sending data onto said bus but said linklayer IC does not send data onto said bus, generates a link releasesignal in order to release the link layer IC bus occupation after apredetermined time period following said grant signal has elapsed.

Advantageous additional embodiments of the inventive method aredisclosed in the respective dependent claim.

In principle the inventive bus interface is suited for transferring datato or from a device to be controlled by the bus, and includes:

a link layer IC for connection to said device;

a physical layer IC for connection to said bus, wherein said physicallayer IC generates a grant signal in order to give to said link layer ICaccess to said bus for sending data onto said bus and wherein, untilsaid link layer IC has finished sending said data onto said busfollowing said grant signal, said link layer IC keeps said bus occupied;

a timer included in said link layer IC which in case said physical layerIC grants to said link layer IC access for sending data onto said busbut said link layer IC does not send data onto said bus, generates alink release signal in order to release the link layer IC bus occupationafter a predetermined time period following said grant signal haselapsed.

Advantageous additional embodiments of the inventive apparatus aredisclosed in the respective dependent claim.

DRAWINGS

Embodiments of the invention are described with reference to theaccompanying drawings, which show in:

FIG. 1 IEEE1394 double-node for bi-directional real-time videoapplications;

FIG. 2 an IEEE1394 bus-connected set-top box, VCR and DVD player;

FIG. 3 a blocked bus;

FIG. 4 a bus in which blocking is prevented.

EMBODIMENTS

In FIG. 1 a first physical layer IC PLI1 is connected via an IEEE1394bus cable connection to a second physical layer IC PLI2 which itself isalso connected to the further IEEE1394 bus cable B. PLI1 is at the otherside assigned to a first link layer IC LLI1 for data input, and PLI2 isassigned to a second link layer IC LLI2 for data output. LLI1 and LLI2are both assigned to the same application device APP. LLI1 and PLI1 viaLLI1 are controlled by a first microcontroller μP1. LLI2 and PLI2 viaLLI2 are controlled by a second microcontroller μP2. Application deviceAPP can be controlled by μP1 and μP2, or by one of them. In both casesμP1 and μP2 may interact with each other (not depicted).

The invention can e.g. be used for an application as depicted in FIG. 2:A set-top box STB with receiving unit RU, MPEG decoder MDEC and IEEE1394interface 1394S receives a digital TV program via satellite or cable.The receiving unit output signal is transmitted via IEEE1394 bus for thepurpose of recording to a video recorder VCRR including also a IEEE1394interface 1394V. Simultaneously, a DVD player DVDP replays a DVD discand the DVD data is also transported via an IEEE1394 bus interface 1394Dto the IEEE1394 bus interface 1394S of the set-top box in order to bedecoded by the MPEG decoder MDEC and to be displayed on the screen of atelevision receiver TV. TV may still have an analog signal connection tothe set-top box, but may also be connected to STB by an IEEE1394 businterface. So, the set-top box IEEE1394 bus node 1394S needs abi-directional functionality.

In FIG. 3 the clock CLK, the status of the physical layer PHST, thestatus LIST of a link layer IC and the bus control BCTL time periods ofthe physical layer and of the link layer IC are depicted. A physicallayer IC grants bus access to a link layer IC by sending a PHYGRT bit orimpulse. Thereafter bus control for sending data is assigned to thatlink layer IC. After sending data onto the bus the link layer IC wouldsignal to the physical layer IC that it needs no longer bus accesswhereupon the physical layer could give access to another devicedemanding bus access. However, as long as the link layer IC does notsend data onto the bus, for example because a user has switched off thatdevice in the meantime, the bus will be blocked for the physical layerIC and for all other devices connected to the bus.

In order to avoid such situation an additional timer function is addedto the link layer IC which sends a link release bit or impulse LIRLafter a predetermined time period, beginning basically with PHYGRT, haselapsed. LIRL is sent in correlation with e.g. slope TLR of clock CLK,as depicted in FIG. 4. As a consequence, the bus control BCTL is givenback to the physical layer. The other details of FIG. 4 correspond tothat of FIG. 3. The corresponding timer TIM is shown in the blockdiagram of FIG. 1.

The invention can also be used to achieve spike protection. It canhappen that the physical layer IC grants unintended bus access to thelink layer IC because of spike signals on control signals of thephysical layer/link layer IC connection. Also in such cases the abovedescribed timer function on the link layer IC ensures that, even thoughthe link layer IC didn't request bus access, the bus is released againby the link layer IC after a predetermined time period has elapsed. Thattime period may differ from the above described time period, accordingto the current application or bus environment. The length of the timeperiod is then controlled by the presence or absence of a prior busrequest from the link layer IC.

What is claimed is:
 1. Method for transferring bus data to or from adevice to be controlled by an IEEE1394 bus, wherein for interfacingbetween said bus and said device a physical layer integrated circuit(“IC”) and a link layer IC are used and wherein, upon request from saidlink layer IC, said physical layer IC generates a grant signal in orderto give to said link layer IC access to said bus for sending data ontosaid bus and wherein, until said link layer IC has finished sending saiddata onto said bus following said grant signal, said bus remains in anoccupied status wherein said link layer IC includes a timer functionwhich, in case said physical layer IC grants upon request from said linklayer IC to said link layer IC access for sending data onto said bus butsaid link layer IC does not send data onto said bus, generates after theelapse of a first predetermined time period following said grant signala link release signal for releasing the current bus occupation by saidlink layer IC and for automatically giving back the bus control to saidphysical layer IC, and wherein, following unintended grant of bus accessto said link layer IC because of spike signals on control signals ofsaid bus, said timer function generates after the elapse of a secondpredetermined time period following said grant signal a link releasesignal for releasing the current bus occupation by said link layer ICand for automatically giving back the bus control to said physical layerIC, and wherein the length of said first or said second time period iscontrolled by the presence or absence of a prior bus request from saidlinklayer IC.
 2. Bus interface for transferring bus data to or from adevice to be controlled by an IEEE1394 bus, including: a link layerintegrated circuit (“IC”) for the connection to said device; a physicallayer IC for the connection to said bus, wherein, upon request from saidlink layer IC, said physical layer IC generates a grant signal in orderto give to said link layer IC access to said bus for sending data ontosaid bus and wherein, until said link layer IC has finished sending saiddata onto said bus following said grant signal, said bus remains in anoccupied status comprising: a timer included in said link layer ICwhich, in case said physical layer IC grants upon request from said linklayer IC to said link layer IC access for sending data onto said bus butsaid link layer IC does not send data onto said bus, generates after theelapse of a first predetermined time period following said grant signala link release signal for releasing the current bus occupation by saidlink layer IC and for automatically giving back the bus control to saidphysical layer IC, and wherein, following unintended grant of bus accessto said link layer IC because of spike signals on control signals ofsaid bus, said timer generates after the elapse of a secondpredetermined time period following said grant signal a link releasesignal for releasing the current bus occupation by said link layer ICand for automatically giving back the bus control to said physical layerIC, and wherein the length of said first or said second time period iscontrolled by the presence or absence of a prior bus request from saidlink layer IC.
 3. Bus interface according to claim 2, including two suchlink layer IC/physical layer IC pairs.